Full-time or contract via CO Consulting, Boulder, Colorado. Keywords: formal
verification, model checking, assertion-based verification, simulation, clock
extraction, FormalCheck, NCSIM, Verilog-XL, TestBuilder, constrained random
simulation, Cadence, Bell Labs, signal integrity, ModelSim, Verilog, VHDL, ASIC,
OVL, Sugar/PSL, System Verilog, Sales engineering, teach, demonstrate, debug,
application notes, UNIX, Windows XP/2000/98, Solaris, Linux, C, Awk, ClearCase,
mentor, communicator, leader.
